As shown in FIG. 1, the conventional stepped signal generating circuit is constituted such that the connection points of serially connected resistances 101-106 are connected to one sides of N-MOS transistors 107-111 which receive digital input clocks 1-5 through their gates, and the other sides of the N-MOS transistors 107-111 are commonly connected to an output terminal 112. In the conventional circuit constituted as described above, the digital clocks 1-5 are digital signals which are outputted sequentially at the same intervals as the input clocks after receipt of digital input clocks of a certain frequency, as shown in FIG. 2A.
The digital clocks 1-5 shown in FIG. 2A are supplied to the gates of the N-MOS transistors 107-111 in order to turn-on/off the N-MOS transistors 107-111. In such a manner that the N-MOS transistors receiving high level digital clocks should be turned on, and that the levels of the output voltages should be varied as shown in FIG. 2B, thereby forming stepped type output voltages. That is, the digital clocks 1-5 in the form of 10000, 01000, 00100, 00010, and 00001 are inputted into the gates of the N-MOS transistors 107-111, with the result that stepped signals are outputted through the output terminal 112.
However, in the conventional stepped signal generating circuit, the power source V.sub.DD is supplied thoroughly the resistances 101-106, and therefore, when the resistance values of the resistances 101-106 are processed. It is difficult to define the resistance values. Not only so, but it is also difficult to design the sizes of the transistors 107-111 in a uniform manner, and therefore, if there is a signal which is delivered to the control gates even slightly late, then an abnormality is generated in the output, thereby making it impossible to form perfect stepped signals.